214 lines
3.9 KiB
Plaintext
214 lines
3.9 KiB
Plaintext
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module uart
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BASEREG EQU #F8EF
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;DLAB=0
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THR EQU BASEREG+#000 ;(W)Transmit Holding Register
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RBR EQU BASEREG+#000 ;(R)Receive Buffer Register
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IER EQU BASEREG+#100 ;(RW)Interrupt Enable Register
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EDSSI EQU %1000 ;Enable Modem Status Interrupt
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ELSI EQU %0100 ;Enable Receiver Line Status Interrupt
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ETBEI EQU %0010 ;Enable Transmitter Holding Register Empty Interrupt
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ERBFI EQU %0001 ;Enable Received Data Available Interrupt
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FCR EQU BASEREG+#200 ;(W)FIFO Control Register
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IIR EQU BASEREG+#200 ;(R)Interrupt Identification Register
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LCR EQU BASEREG+#300 ;(RW)Line Control Register
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DLAB EQU %10000000 ;Divisor Latch Access Bit
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SETBRK EQU %01000000 ;Set Break
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STKPAR EQU %00100000 ;Stick Parity
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EPS EQU %00010000 ;Even Parity Select
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PEN EQU %00001000 ;Parity Enable
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STB EQU %00000100 ;Number of Stop Bits
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WLSB1 EQU %00000010 ;Word Length Select #1
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WLSB0 EQU %00000001 ;Word Length Select #0
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MCR EQU BASEREG+#400 ;(RW)Modem Control Register
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RTS EQU %10 ;Request to Send
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DTR EQU %01 ;Data Terminal Ready
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LSR EQU BASEREG+#500 ;(RW)Line Status Register
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FIFOE EQU %10000000 ;Error in Receiver FIFO
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TEMT EQU %01000000 ;Transmitter Empty
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THRE EQU %00100000 ;Transmitter Holding Register Empty
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BI EQU %00010000 ;Break Interrupt (BI)
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FE EQU %00001000 ;Framing Error (FE)
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PE EQU %00000100 ;Parity Error (PE)
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OE EQU %00000010 ;Overrun Error (OE)
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DR EQU %00000001 ;Data Ready (DR)
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MSR EQU BASEREG+#600 ;(RW)Modem Status Register
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DCD EQU %10000000 ;Data Carrier Detect
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RI EQU %01000000 ;Ring Indicator
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DSR EQU %00100000 ;Data Set Ready
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CTS EQU %00010000 ;Clear To Send
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DDCD EQU %00001000 ;Delta Data Carrier Detect
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TERI EQU %00000100 ;Trailing Edge Ring Indicator
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DDSR EQU %00000010 ;Delta Data Set Ready
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DCTS EQU %00000001 ;Delta Clear To Send
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SCR EQU BASEREG+#700 ;(RW)Scratch Register
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;DLAB=1
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DLL EQU BASEREG+#000 ;(RW)Divisor Latch LSB
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DLH EQU BASEREG+#100 ;(RW)Divisor Latch MSB
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;eRS232 for ZX-Evo
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ERS_DR EQU #00EF
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ERS_SR EQU #C2EF
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ERS_ST EQU #C3EF
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ERS_CR EQU #C7EF
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;set baud rate
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;hl=divider
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SetBaud
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ld bc,LCR
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in a,(c):or DLAB:out (c),a ;set DLAB=1
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ld b,high DLL
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out (c),l ;low
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inc b
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out (c),h ;high
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ld b,high LCR
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in a,(c):and !DLAB:out (c),a ;set DLAB=0
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ld b,high ERS_CR
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ld a,#F1
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out (c),a
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ld a,#07
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out (c),a
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ret
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;set line control register
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;a=status
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SetLineControl
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ld bc,LCR
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out (c),a
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ret
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;put char
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;a=char
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PutChar
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ld bc,ERS_ST
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exa
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pc1 in f,(c):jr z,pc1 ;wait for room
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exa
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ld b,high ERS_DR
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out (c),a
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ret
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;get char
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;out: a=char
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GetChar
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ld bc,ERS_SR
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gc1 in f,(c):jr z,gc1 ;wait for data
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ld b,high ERS_DR
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in a,(c)
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ret
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;write block
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;hl=buffer addr
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;bc=len
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Write
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ld d,b
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ld e,c
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ww1 ld bc,ERS_ST
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in c,(c)
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jr z,ww1
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ld a,d
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or a
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jr nz,ww2
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ld a,e
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cp c
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jr nc,ww2
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ld c,e
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ww2 ex de,hl
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xor a
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ld b,a
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sbc hl,bc
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ex de,hl
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ld b,c
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ld c,low ERS_DR
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otir
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ld a,d
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or e
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jr nz,ww1
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ret
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;read block
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;hl=buffer addr
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;bc=len
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Read
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ld d,b
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ld e,c
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rr1 ld bc,ERS_SR
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in c,(c)
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jr z,rr1
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ld a,d
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or a
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jr nz,rr2
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ld a,e
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cp c
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jr nc,rr2
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ld c,e
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rr2 ex de,hl
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xor a
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ld b,a
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sbc hl,bc
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ex de,hl
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ld b,c
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ld c,low ERS_DR
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inir
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cable_cancel_download ld a,0
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or a
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jp nz,cable_cancel_download_ex
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ld a,d
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or e
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jr nz,rr1
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ret
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;;read block fast
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;;hl=buffer addr
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;;bc=len
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;Readf push hl:exx:pop hl
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; ld de,high LSR+256*high RBR ;+256
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;
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; ld c,low LSR
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;r0_ dup 16
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; ld b,e
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; in a,(c):and DR:jr z,$-4 ;wait
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;
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; ld b,d:ini
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; edup
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; exx
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; dup 16
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; dec bc
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; edup
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; ld a,b:or c
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; exx
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; jp nz,r0
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; ret
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endmodule
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